********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*May 26, 2014
*ECN S14-1102, Rev. B
*File Name: Si8472DB_PS.txt and Si8472DB_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si8472DB D G S 
M1 3 GX S S NMOS W= 567986u  L= 0.25u 
M2 S GX S D PMOS W= 567986u L= 2.024e-07 
R1 D 3 2.675e-02 TC=4.293e-03 1.845e-06 
CGS GX S 4.539e-10 
CGD GX D 2.012e-11 
RG G GY 5.3 
RTCV 100 S 1e6 TC=-1.897e-04 1.584e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 1.7e-8 
+ RS = 9.557e-03 KP = 6.771e-05 NSUB = 1.629e+17 
+ KAPPA = 4.772e-01 ETA = 1.000e-07 NFS = 7.569e+11 
+ LD = 0 IS = 0 TPG = 1) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 1.7e-8 
+NSUB = 4.100e+16 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.022e-08 T_MEASURED = 25 BV = 21 
+RS = 1.000e-01 N = 1.006e+00 IS = 3.549e-10 
+EG = 7.811e-01 XTI = 1.964e+00 TRS1 = 1.151e-03 
+CJO = 2.310e-10 VJ = 4.687e-01 M = 3.322e-01 ) 
.ENDS 
